SMSC LAN9311i manuales

Smsc LAN9311i Manual de usuario (460 paginas)

Marca: Smsc | Categoria: Accesorios De Computador | Tamaño: 4.49 MB |

Inglés

Tabla de contenidos

LAN9311/LAN9311i

1

Two Port 10/100 Managed

1

Ethernet Switch with 16-Bit

1

Non-PCI CPU Interface

1

Table of Contents

3

DATASHEET

10

List of Figures

12

List of Tables

14

Chapter 1 Preface

16

1.2 Buffer Types

18

1.3 Register Nomenclature

19

Chapter 2 Introduction

20

2.2 Block Diagram

21

2.2.3 Switch Fabric

23

2.2.4 Ethernet PHYs

23

2.2.6 Host MAC

24

2.2.8 1588 Time Stamp

24

2.3 System Configuration

25

3.1 Pin Diagrams

26

128-XVTQFP

27

3.2 Pin Descriptions

28

EEPROM_SIZE_1

31

EEPROM_SIZE_0

32

PHY_ADDR_SEL

32

4.1 Clocks

36

4.2 Resets

36

4.2.1 Chip-Level Resets

37

4.2.2 Multi-Module Resets

38

4.2.3 Single-Module Resets

39

4.2.4 Configuration Straps

40

4.3 Power Management

46

Chapter 5 System Interrupts

49

5.2.3 Ethernet PHY Interrupts

52

5.2.4 GPIO Interrupts

52

5.2.5 Host MAC Interrupts

52

5.2.8 Software Interrupt

54

5.2.9 Device Ready Interrupt

54

Chapter 6 Switch Fabric

55

6.2.2 Switch Fabric CSR Reads

57

6.3 10/100 Ethernet MACs

60

6.3.2 Transmit MAC

62

6.4 Switch Engine (SWE)

63

6.4.2 Forwarding Rules

66

6.4.4 VLAN Support

70

6.4.5 Spanning Tree Support

70

6.4.7 Broadcast Storm Control

74

6.4.9 Port Mirroring

75

6.4.11 Counters

76

6.5 Buffer Manager (BM)

77

6.5.7 Counters

81

Chapter 7 Ethernet PHYs

82

7.2 Port 1 & 2 PHYs

83

7.2.1 100BASE-TX Transmit

84

7.2.2 100BASE-TX Receive

87

7.2.3 10BASE-T Transmit

89

7.2.4 10BASE-T Receive

89

7.2.5 PHY Auto-negotiation

90

7.2.6 HP Auto-MDIX

93

7.2.7 MII MAC Interface

93

7.2.8 PHY Management Control

94

7.2.9 PHY Power-Down Modes

94

7.2.10 PHY Resets

95

7.3 Virtual PHY

96

7.3.2 Virtual PHY Resets

98

8.1 Functional Overview

99

8.2 Host Memory Mapping

99

8.3 Host Data Bus

99

8.4 Host Endianess

100

8.5 Host Interface Timing

102

8.5.4 PIO Reads

107

8.5.5 PIO Burst Reads

108

8.5.8 PIO Writes

111

8.6 HBI Interrupts

112

9.1 Functional Overview

113

9.2 Flow Control

114

9.4 Address Filtering

115

9.4.1 Perfect Filtering

116

9.4.2 Hash Only Filtering

116

9.4.3 Hash Perfect Filtering

116

9.5 Wake-up Frame Detection

117

9.5.1 Magic Packet Detection

119

9.6 Host MAC Address

120

9.7 FIFOs

121

9.8 TX Data Path Operation

123

9.8.1 TX Buffer Format

125

9.8.2 TX Command Format

125

9.8.3 TX Data Format

127

9.8.4 TX Status Format

128

9.8.6 Transmit Examples

129

9.8.7 Transmitter Errors

132

9.9 RX Data Path Operation

133

9.9.2 RX Packet Format

135

9.9.3 RX Status Format

136

9.9.5 Receiver Errors

137

10.1 Functional Overview

138

10.2 I

138

10.2.2 I

140

C EEPROM

140

10.2.3 Microwire EEPROM

145

10.2.4 EEPROM Loader

150

11.1 Functional Overview

155

11.1.2 Block Diagram

156

11.2 IEEE 1588 Time Stamp

157

11.2.1 Capture Locking

158

11.2.2 PTP Message Detection

159

11.3 IEEE 1588 Clock

160

11.4 IEEE 1588 Clock/Events

161

11.5 IEEE 1588 GPIOs

161

11.6 IEEE 1588 Interrupts

161

12.1 General Purpose Timer

162

12.2 Free-Running Clock

162

13.1 Functional Overview

163

13.2 GPIO Operation

163

13.2.2 GPIO Interrupts

164

13.3 LED Operation

165

14.1 TX/RX FIFO Ports

168

14.2.1 Interrupts

173

14.2.2 Host MAC & FIFO’s

181

14.2.3 GPIO/LED

193

14.2.4 EEPROM

198

14.2.5 IEEE 1588

202

14.2.6 Switch Fabric

230

14.2.8 Virtual PHY

246

14.2.9 Miscellaneous

260

14.4.1 Virtual PHY Registers

287

0 0 Manual mode, no crossover

305

0 1 Manual mode, crossover

305

1 0 Auto-MDIX mode

305

14.5.1 General Switch CSRs

320

14.5.3 Switch Engine CSRs

368

14.5.4 Buffer Manager CSRs

413

15.2 Operating Conditions**

442

15.3 Power Consumption

443

15.4 DC Specifications

444

15.5 AC Specifications

445

15.5.4 PIO Read Cycle Timing

448

15.5.8 PIO Write Cycle Timing

452

15.5.10 Microwire Timing

454

15.6 Clock Circuit

455

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